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W51300 flash vr controller publication release date: april 1997 - 1 - revision a 2 general description the W51300 is a voice recorder ic which contains a/d and d/a converters to digitize and reproduce voice signals. an anti-alias/smoothing filter, agc circuit, mic preamplifier, and speaker power amplifier are used to smooth the input voice and set the output voice to a certain volume while minimizing the number of extra components needed . the recording time depends on the size of the external memory. the external memory is a nonvolatile flash eprom that stores the voice data while power is switched off. this external memory provides a great advantage in cartridge or greeting card applications. a maximum of 16 mbit of memory can be cascaded. in addition , the W51300's flexible segmentation, selective recording/erasing, forward and backward move functions , and mcu interface provide flexibility to meet the needs of a wide variety of applications. features modified adm algorithm with 24 khz sampling frequency when r osc = 620 k w operates with winbond serial flash eprom built-in a/d, d/a, mic preamplifier, agc circuit, anti-alias/smoothing filter, speaker power amplifier, and led indicator 8 input trigger pins (l_rec, e_play, l_play, fwd, bwd, stop, erase, reset) debounced to ensure noise-free operations single/ m ulti-voice segment operation, n ormal/cpu mode selected by pin option (smode, cpu) cascadable for longer duration by directly cascading serial flash eprom s (maximum 16 mbits) maximum 63 voice segments available in multi-segment operation provides selective record, erase , and playback functions provides low power detection circuit at 3. 0v provides both speaker dire ct drive and speaker current output (5 ma) low power consumption: - operating: 15 ma (typ.) - standby: 0.01 m a (typ.)
W51300 - 2 - pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 16 14 15 24 25 26 27 28 20 21 22 23 17 18 19 32 31 30 29 test agc bwd stop eop fwd reset vccd clk extclk micref mic osc aud vssd vssa spk+ spk- vcca addr busy led data ctrl mode cpu smode l_rec l_play e_play erase vcca pin description no. pin i/o description 1 bwd i/o message backward control pin in normal mode output clock signal (to mcu) in cpu mode 2 stop i stop playback control pin in normal mode input clock signal (from mcu) in cpu mode 3 eop i end of page process signal (from flash eprom ) 4 clk o data clock pin for flash eprom 5 addr o address clock pin for flash eprom 6 data i/o bidirectional data pin for flash eprom 7 ctrl o control signal for flash eprom 8 mode o mode control pin for flash eprom
W51300 publication release date: april 199 7 - 3 - revision a 2 pin description, continued no. pin i/o description 9 busy o output busy signal, high during playback 10 led o blink (flash (volume-controlled) during playback flash blink (3 hz) when during low battery is low, segment full, or memory full on during recording, erasing, and memory formatting 11 v ssd - digital negative power supply 12 v ssa - analog negative power supply 13 spk- o speaker voltage output - 14 spk+ o speaker voltage output + 15 v cca - analog positive power supply 16 aud o speaker current output (maximum 5 ma when v cc = 4.5 v) 17 v cca - analog positive power supply + 18 osc i oscillation frequency control pin 19 micref i microphone reference 20 mic i microphone input 21 agc i automatic gain control input 22 v ccd - digital positive power supply 23 cpu i normal/cpu mode select pin: low for normal, high for cpu 24 smode i multi/ s ingle segment select pin: low for multi, high for single 25 test i external test pin for testing 26 extclk i external clock pin for testing 27 reset i reset control pin 28 l_rec i level record control pin 29 l_play i level playback control pin 30 e_play i edge playback control pin 31 erase i message erase control pin in normal mode input level signal (from mcu) in cpu mode 32 fwd i/o message forward control pin in normal mode output level signal (to mcu) in cpu mode
W51300 - 4 - block diagram agc amp anti-alias/ smoothing filter adm modulator power amp logic/timing controller mic micref agc spk+ spk- flash eeprom interface data clk addr eop ctrl mode smode cpu aud aud amp busy vccd vssd vcca vssa l_rec l_play reset led osc test extclk e_play erase stop fwd bwd mcu interface functional description 1. single/ m ulti-segment operation the W51300 is typically used for either single or multi-segment operations. single or multi-segment operating mode is selected by pin option. single segment the smode pin should be connect ed to v cc . in this mode, only one voice segment can be recorded. the storage duration can be extended by cascading serial flash eprom s; up to 16 mbits of memory can be cascaded. multi-segment the smode pin should be connect ed to v ss or left floating. in this mode, a maximum of 63 voice segments can be recorded into flash eprom s; up to 16 mbits of memory can be cascaded. messages can easily be accessed by using the fwd, bwd , and play pins. 2. selective record when the system is operated in multi-segment mode, voice segment s can be recorded selectively. u sers can insert a voice segment between any two existing voice segments. for instance, suppose there are already five voice segments , 1, 2, 3, 4, and 5, and the cap (current address/message pointer) is at 3 . then a newly record ed voice segment will be assigned the number 4, and the original segment s 4 and 5 will be changed to 5 and 6 , respectively . if the maximum number of voice segments (63) or the end of memory space has been reached , a press of l_rec will be invalid and the led will flash at 3 h z for 2 seconds to indicate the invalid action.
W51300 publication release date: april 199 7 - 5 - revision a 2 3. selective erase when the system is operated in multi-segment mode, voice segments can be erased selectively instead of sequentially. users can play the voice segments one by one until they reach the segment to be erased, and then stop playing and press the erase key . the current voice segment will be erased and the cap value will be change d to the previous voice segment. the led will light during the erasing procedure to indicate that the system is busy, and all input triggers will be disabled except for reset. 4. chip erase p ress ing and holding the reset key for more than two seconds will clear all data in the flash eprom . 5. function keys in normal mode, eight input trigger pins with built-in debounce circuit ry are used to operate the W51300. these eight pins are described below. l_rec l_rec is an active - high, level-triggered recording pin with an internal 500 k w pull - low resistor . when this pin goes high, the device starts recording and continues until this pin is released or the end of the memory space is reached . when the memory or segment is full , this pin is invalid. e_play e_play is an active-high, edge-triggered playback pin with an internal 500 k w pull - low resistor . in single segment operation, the toggle stop function is enabled. this means a debounced rising edge on e_play during voice playing will stop the ongoing playback operation immediately. in multi- segment operation, the toggle skip function is enabled. this means a debounced rising edge on e_play during voice playing will cause the device to skip to the next voice segment. a rising edge on this pin while the last voice segment is being played will cause the device to skip to the first voice segment . this function is useful for fast scanning through a series of messages. l_ play l_play is an active-high, level-triggered playback pin with an internal 500 k w pull - low resistor . the current voice segment will be played back when this pin is pressed. a concatenated loop playing function is enabled to link all messages in a row and loop back to the first message when the last message is reached. stop this is an active-high, edge-triggered stop pin with an internal 500 k w pull-low resistor . pressing this pin immediately stops playback of the on going message . this pin is enabled only while a voice is playing. erase erase is an active-high, edge-triggered erase pin with an internal 500 k w pull-low resistor . pressing this pin erases the current voice segment without affecting the content of the other segments . fwd this is an active-high, edge-triggered forward pin with an internal 500 k w pull-low resistor . p ress ing this pin for less than 1 second moves the cap from the current voice segment to the next one. pressing this pin for more than 1 second move s the cap from the current voice segment to the last one.
W51300 - 6 - bwd this is an active-high, edge-triggered backward pin with an internal 500 k w pull-low resistor . pressing this pin for less than 1 second move s the cap from the current voice segment to the previous one. p ress ing this pin for more than 1 second move s the cap from the current voice segment to the first one. reset this is an active-high, edge-triggered reset pin with an internal 500 k w pull-low resistor . pressing this pin for less than 2 seconds causes the system power - on initialization procedure to be executed and reset s the message pointer to 1. pressing this pin for more than 2 seconds execute s the c hip erase procedure , so that all of the recorded messages are cleared. 6. low battery warning a low battery warning function is provided to protect the recorded voice messages from being lost due to loss of power . before a recording, erasing , or reset operation, the battery voltage will be checked . if the voltage falls to 3 volts or below , all operations except the led stop, and the led flash es at 3 hz for 2 seconds to indicate that the battery is low . 7. speaker output the W51300 provides two types of speaker drivers, direct drive and current output. the direct drive is a voltage output from the built-in power amplifier. t his output can be used to drive a speaker directly without any extra components, such as resistor s or transistor s . the maximum driving current is 56 ma (rms) when the output is connected to a 16 w speaker. the current output is the same as that of the standard speaker driver used in most winbond powerspeech tm chips . the m aximum driving current is 5 ma when v cc = 4.5 v . 8. sampling frequency adjustment t he external r osc can be adjusted to change the system clock (f osc ) and sampling frequency (fs). the relationship between f osc and fs is fs = f osc /32. the relationship between fs and r osc is shown is the figure below. 0 5 10 15 20 25 30 35 0 200 400 600 800 1,000 1,200 1,400 1,600 1,800 2,000 2,200 2,400 2,600 2,800 3,000 3,200 rosc (kohm) fs (khz)
W51300 publication release date: april 199 7 - 7 - revision a 2 9. mcu interface in cpu mode, five pins can be used as an mcu interface to communicate with external micro- controllers by the counter method. reset, erase, stop are configured as input pins , while fwd and bwd are configured as output pins. the application diagram is shown below. pin 1 pin 2 pin 3 pin 4 erase stop fwd bwd microcontroller W51300 pin 0 reset the W51300 offers 10 operati n g modes that can be controlled by a microcontroller . the rising edge of pin 1 informs the W51300 to begin to count the pulses generated on pin 2, and the falling edge of pin 1 informs the W51300 to latch the pulse number. then the number of pulses is decoded to instruct the W51300 to perform various operations . the operati n g modes and the corresponding waveforms are shown below. . . . t t1 pin 1 pin 2 note: t is 5 m s minimum at f osc = 768 khz. t1 is 10 m s minimum at f osc = 768 khz. item mode name number of pulses on pin 2 1 record 1 2 play 2 3 erase 3 4 stop (for r ecord and p lay) 4 5 memory reset 5 6 system reset 6 7 read cap (current address pointer) 7
W51300 - 8 - continued item mode name number of pulses on pin 2 8 read asn (available segment number) 8 9 store 4 bytes data to flash eprom 9 10 read 4 bytes data from flash eprom 10 after receiving a command from the microcontroller, the W51300 will send back a corresponding response , as shown below. . . . t1 t1 t1 pin 3 pin 4 note: t1 is 5 msec at f osc = 768 khz. item mode name number of pulses generated on pin 4 1 accept 0 2 error: low battery 1 3 error: memory full 2 4 error: out of segment s 3 5 error: wrong cap 4 6 unknown mode 5 7 unknown error 6 when pin 3 is low and pin 4 is high, the W51300 is busy. absolute maximum ratings parameter symbol condition rated value unit operating temp. t opr - 0 to +70 c storage temp. t stg - -55 to +150 c power supply v cc - v ss - -0.3 to +7.0 v input dc voltage v in all pins v ss -0. 3 to v cc + 0 . 3 v note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device.
W51300 publication release date: april 199 7 - 9 - revision a 2 dc characteristics (v cc = 5v, v cc = 0v, t a = 25 c) parameter sym. conditions limits unit min. typ. max. operating voltage v cc - 3.0 4.5 5.5 v standby current i sb all inputs = gnd d ata = 5v 0 0.01 1 m a operating current i op no load - 15 25 ma input voltage high v ih all input pins 2.0 - - v low v il - - 0.8 v input low current i il v in = 0 v 0 - 1 m a in put high current d igital pins i ih 1 v in = 5 v 5 8 12 m a a nalog pins, mic i ih2 v in = 5 v 0.8 1 1.2 ma smode, cpu i ih3 v in = 5 v - - 1 m a test, ext c lk i ih 4 v in = 5 v 50 75 100 m a output low current addr, clk, mode, ctrl, data i ol1 v out = 0.5 v 0.5 1.5 3 ma led, busy i ol2 v out = 0.5 v 6 10 15 ma output high current addr, clk, mode, ctrl, data i o h 1 v o ut = 4 .5 v - 0.5 - 1.5 - 3 ma led, busy i o h 2 v o ut = 4 .5 v - 2.5 -4.5 -6. 5 ma oscillation frequency f osc r osc = 620 k w 6 1 0 768 92 0 khz
W51300 - 10 - ac characteristics ( v cc = 5v, v ccs = 0v, t a = 25 c) parameter sym. conditions limits unit min. typ. max . input debounce time normal mode t deb1 f osc = 768 khz 21 32 42.7 ms cpu mode t deb2 1.27 1.9 2.54 m s clk duty cycle write t clk1 - - 50 - % read t clk2 - - 75 - % clk frequency write f clk1 f osc = 768 khz - 384 - khz read f clk2 - 192 - khz addr duty cycle t addr - - 50 - % addr frequency f addr f osc = 768 khz - 384 - khz input clock duty cycle of erase pin t in cpu mode 40 - 60 % input clock frequency of erase pin f in cpu mode - - 100 khz out put clock duty cycle of bwd pin t out cpu mode - 50 - % out put clock frequency of bwd pin f out cpu mode , f osc = 768 khz - 100 hz analog circuit characteristics (v cc = 5v, v ss = 0v, t a = 25 c) parameter sym. conditions limits unit min. typ. max. mic input voltage v mic peak to peak - - 20 mv mic input resistance r mic - - 10 - k w passband of lpf bw f osc = 768 khz - 3.5 - khz speaker output power p out r ext = 16 w , rms - - 50 mw speaker voltage output v out r ext = 600 w - - 1.2 v p-p speaker current output i aud v cc = 4.5 v, r l = 100 w -4.0 -5.0 -6.0 ma speaker resistance r sp - 8 16 - w
W51300 publication release date: april 199 7 - 11 - revision a 2 typical application circuit (for reference only) l_rec e_play osc vccd vcca vssd vssa spk+ spk- mic micref agc 8/16 speaker v rosc mic c1 r1 c3 c4 W51300 r2 r3 c2 w data ctrl clk addr eop mode vcc v w55fxx data ctrl clk addr eop mode erase reset led r4 smode cpu component list: r2 = 1 k r1 = 470 k r3 = 8.2 k r4 = 220 w w w w c2 = 2.2 f c3 = c4 = 0.22 f m m rosc = 620 k w c1 = 4.7 f m fwd bwd l_play stop cd ss dd cd r5 r5 = 5.1 k w cd = 0.1 f m notes: 1. r1 and c1 can be adjusted for different agc attack time and release time. 2. set c3 = c4 to reduce ground noise.
W51300 - 12 - headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792697 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-7197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-7190505 fax: 886-2-7197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27516023 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2730 orchard parkway, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-9436668 note: all data and specifications are subject to change without notice.

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